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| XM28C040 4 Megabit Module XM28C040 5 Volt, Byte Alterable E2PROM DESCRIPTION 512K x 8 Bit TYPICAL FEATURES * * * * * * * * * * High Density 4 Megabit (512K x 8) Module Access Time of 200ns at -55C to +125C Base Memory Component: Xicor X28C010 Pinout Conforms to JEDEC Standard for 4 Megabit E2PROM Fast Write Cycle Times --256 Byte Page Write Early End of Write Detection --DATA Polling --Toggle Bit Polling Software Data Protection Three Temperature Ranges --Commercial: 0C to +75C --Industrial: -40 to +85C --Military: -55 to +125C High Rel Modules all Components are MIL-STD-883 Compliant Endurance: 100,000 Cycles The XM28C040 is a high density 4 Megabit E2PROM comprised of four X28C010's mounted on a co-fired multilayered ceramic substrate. Individual components are 100% tested prior to assembly in module form and then 100% tested after assembly. The XM28C040 is configured 512K x 8 bit. The module supports a 256-byte page write operation. This combined with DATA Polling or Toggle Bit Polling, effectively provides a 39s/byte write cycle, enabling the entire array to be rewritten in 10 seconds. The XM28C040 provides the same high endurance and data retention as the X28C010. FUNCTIONAL DIAGRAM X28C010 A0-A16 I/O0-I/O7 OE WE CE X28C010 A0-A16 I/O0-I/O7 OE WE CE PIN CONFIGURATION A18 A16 A15 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 XM28C040 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/04 I/O3 A0-A16 I/O0-I/O7 OE WE CE A18 A17 X28C010 A0-A16 I/O0-I/O7 OE WE CE X28C010 A0-A16 I/O0-I/O7 OE WE CE A2 A1 A0 I/O0 I/O1 I/O2 VSS 3873 FHD F02 3873 FHD F01 (c) Xicor, Inc. 1991-1997 Patents Pending 3873-1.7 6/13/97 T1/C0/D0 SH 1 Characteristics subject to change without notice XM28C040 PIN DESCRIPTIONS Addresses (A0-A18) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced (see Note 4). Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/Data Out (I/O0-I/O7) Data is written to or read from the XM28C040 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the XM28C040. PIN NAMES Symbol A0-A18 I/O0-I/O8 WE CE OE VCC VSS NC Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect 3873 PGM T01 2 XM28C040 DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The XM28C040 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms (see Note 4). Page Write Operation The page write feature of the XM28C040 allows the entire memory to be written in 10 seconds. Page write allows two to 256 bytes of data to be consecutively written to the XM28C040 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A8 through A18) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to 255 bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host The XM28C040 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the XM28C040, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Note: If the XM28C040 is in the protected state and an illegal write operation is attempted, DATA Polling will not operate. Toggle Bit (I/O6) The XM28C040 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle from "1" to "0" and "0" to "1" on subsequent attempts to read the last byte written. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations. continues to access the device within the byte load cycle time of 100s. Write Operation Status Bits The XM28C040 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. DATA Polling (I/O7) Figure 1. Status Bit Assignment I/O DP TB 5 4 3 2 1 0 RESERVED TOGGLE BIT DATA POLLING 3873 FHD F09 3 XM28C040 DATA POLLING I/O7 Figure 2. DATA Polling Bus Sequence LAST WRITE WE CE OE VIH I/O7 HIGH Z VOL An An An An An An An 3873 FHD F10 VOH READY A0-A18 Figure 3. DATA Polling Software Flow DATA Polling can effectively halve the time for writing to the XM28C040. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implementing the routine. WRITE DATA WRITES COMPLETE? YES SAVE LAST DATA AND ADDRESS NO READ LAST ADDRESS IO7 COMPARE? YES NO READY 3873 FHD F11 4 XM28C040 THE TOGGLE BIT I/O6 Figure 4. Toggle Bit Bus Sequence LAST WRITE WE CE OE I/O6 VOH * VOL HIGH Z * READY * Beginning and ending state of I/O6 will vary. 3873 FHD F12 Figure 5. Toggle Bit Software Flow The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple XM28C040 memories that is frequently updated. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for testing the Toggle Bit. LAST WRITE LOAD ACCUM FROM ADDR n COMPARE ACCUM WITH ADDR n COMPARE OK? YES NO READY 3873 FHD F13 5 XM28C040 HARDWARE DATA PROTECTION The XM28C040 provides three hardware features that protect nonvolatile data from inadvertent writes. * Noise Protection--A WE pulse less than 10ns will not initiate a write cycle. * Default VCC Sense--All functions are inhibited when VCC is 3V. * Write Inhibit--Holding OE LOW will prevent an inadvertent write cycle during power-up and power-down. SOFTWARE DATA PROTECTION The XM28C040 does provide the Software Data Protection (SDP) feature. The module is shipped from Xicor with the Software Data Protection NOT ENABLED; that is, the module will be in the standard operating mode. In this mode, data should be protected during power-up/-down operations through the use of external circuits. The host system will then have open read and write access of the module once VCC is stable. The module can be automatically protected during powerup/-down without the need for external circuits by employing the SDP feature. The internal SDP circuit is enabled after the first write operation utilizing the SDP command sequence. When this feature is employed, it will be easiest to incorporate in the system software if the module is viewed as a subsystem composed of four discrete memory devices with an address decoder (see Functional Diagram). In this manner, system memory mapping will extend onto the module. That is, the discrete memory ICs and decoder should be considered memory board components and SDP can be implemented at the component level as described in the next section. SOFTWARE COMMAND SEQUENCE A17 and A18 are used by the decoder to select one of the four LCCs. Therefore, only one of the four memory devices can be accessed at one time. In order to protect the entire module, the command sequence must be issued separately to each device. Enabling the software data protection mode requires the host system to issue a series of three write operations: each write operation must conform to the data and address sequence illustrated in Figures 6 and 7. Because this involves writing to a nonvolatile bit, the device will become protected after tWC has elapsed. After this point in time devices will inhibit inadvertent write operations. Once in the protected mode, authorized writes may be performed by issuing the same command sequence that enables SDP, immediately followed by the address/data combination desired. The command sequence opens the page write window enabling the host to write from one to 256 bytes of data. Once the data has been written, the device will automatically be returned to the protected state. In order to facilitate testing of the devices the SDP mode can be deactivated. This is accomplished by issuing a series of six write operations: each write operation must conform to the data and address sequence illustrated in Figures 8 and 9. This is a nonvolatile operation, and the host will have to wait a minimum tWC before attempting to write new data. 6 XM28C040 SOFTWARE DATA PROTECTION Figure 6. Timing Sequence--Byte or Page Write VCC 0V DATA ADDR. A0-A16* CE tBLC MAX WE AA 5555 55 2AAA A0 5555 WRITES OK BYTE OR PAGE (VCC) tWC WRITE PROTECTED *A17 & A18 select one of four devices on the module. 3873 FHD F14 Figure 7. Write Sequence for Software Data Protection Regardless of whether the device has previously been protected or not, once the software data protected algorithm is used and data has been written, the device will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the device will be write protected during power-down and after any subsequent power-up. WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA A0 TO ADDRESS 5555 BYTE/PAGE LOAD ENABLED WRITE DATA XX TO ANY ADDRESS WRITE LAST BYTE TO LAST ADDRESS AFTER tWC RE-ENTERS DATA PROTECTED STATE 3873 FHD F15 7 XM28C040 RESETTING SOFTWARE DATA PROTECTION Figure 8. Reset Software Data Protection Timing Sequence VCC DATA ADDR. A0-A16* CE AA 5555 55 2AAA 80 5555 AA 5555 55 2AAA 20 5555 tWC STANDARD OPERATING MODE WE *A17 & A18 select one of four devices on the module. 3873 FHD F16 Figure 9. Software Sequence to Deactivate Software Data Protection WRITE DATA AA TO ADDRESS 5555 In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the device will be in standard operating mode. WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 80 TO ADDRESS 5555 SYMBOL TABLE WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A 3873 FHD F17 OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 20 TO ADDRESS 5555 8 XM28C040 SYSTEM CONSIDERATIONS Because the XM28C040 is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus. Because the XM28C040 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1F high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. In addition, it is recommended that a 4.7F electrolytic bulk capacitor be place between VCC and VSS for every two modules employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. 9 XM28C040 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................. -65C to +135C Storage Temperature ....................... -65C to +150C Voltage on any Pin with Respect to VSS ................................................ -1V to +7V D.C. Output Current ............................................. 5mA Lead Temperature (Soldering, 10 seconds) .............................. 300C *COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. D.C. OPERATING CHARACTERISTICS XM28C040 TA = 0C to +70C, VCC = +5V 10%, unless otherwise specified. XM28C040I TA = -40C to +85C, VCC = +5V 10%, unless otherwise specified. XM28C040M TA = -55C to +125C, VCC = +5V 10%, unless otherwise specified. Limits Symbol ICC Parameter VCC Current (Active) (TTL Inputs) Min. Max. 80 Units mA Test Conditions CE = OE = VIL, WE = VIH, All I/O's = Open, 1 Device Active Address Inputs = TTL Levels @ f = 5MHz CE, A17, A18 = VCC -0.3V All other inputs = VIH All I/Os = OPEN VIN = VSS to VCC VOUT = VSS to VCC, CE = VIH ISB VCC Current (Standby) 5 mA ILI ILO VlL VIH VOL VOH Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage -1 2 2.4 10 10 0.8 VCC + 1 0.4 A A V V V V IOL = 2.1mA IOH = -400A 3873 PGM T02.2 POWER-UP TIMING Symbol tPUR(2) tPUW(2) Parameter Power-up to Initiation of Read Operation Power-up to Initiation of Write Operation Typ.(1) 100 5 Units ms ms 3873 PGM T03 CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V Symbol CI/O(2) CIN(2) Parameter Input/Output Capacitance Input Capacitance Max. 50 50 Units pF pF Test Conditions VI/O = 0V VIN = 0V 3873 PGM T04.1 Notes: (1) Typical values are for TA = 25C and nominal supply voltage. (2) This parameter is periodically sampled and not 100% tested. 10 XM28C040 A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load 0V to 3V 10ns 1.5V 1 TTL Gate and CL = 100pF 3873 PGM T05.1 MODE SELECTION CE L L H X X OE L H X L X WE H L X X H Mode Read Write Standby and Write Inhibit Write Inhibit Write Inhibit I/O DOUT DIN High Z -- -- Power Active Active Standby -- -- 3873 PGM T06 A.C. CHARACTERISTICS XM28C040 TA = 0C to +75C, VCC = +5V 10%, unless otherwise specified. XM28C040I TA = -40C to +85C, VCC = +5V 10%, unless otherwise specified. XM28C040M TA = -55C to +125C, VCC = +5V 10%, unless otherwise specified. Read Cycle Limits XM28C040-20 Symbol tRC tCE tAA tOE tLZ(4) tOLZ(4) tHZ(4) tOHZ(4) tOH Parameter Min. Read Cycle Time 200 Chip Enable Access Time Address Access Time Output Enable Access Time CE Low to Active Output 0 OE Low to Active Output 0 CE High to High Z Output OE High to High Z Output Output Hold From Address Change 0 Max. 200 200 80 0 0 100 100 0 100 100 0 XM28C040-25 Min. 250 Max. 250 250 100 0 0 100 100 XM28C040 Min. 300 Max. 300 300 100 Units ns ns ns ns ns ns ns ns ns 3873 PGM T07 Read Cycle tRC ADDRESS tCE CE tOE OE WE VIH tOLZ tLZ DATA I/O HIGH Z DATA VALID tAA Note: (3) tOHZ tOH tHZ DATA VALID 3873 FHD F03 tHZ and tOHZ are measured from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven. 11 XM28C040 Write Cycle Limits Symbol tWC tAS tAH tCS tCH tCW tOES tOEH tWP tWPH tDV tDS tDH tDW tBLC Parameter Write Cycle Time Address Setup Time Address Hold Time Write Setup Time Write Hold Time CE Pulse Width OE High Setup Time OE High Hold Time WE Pulse Width WE High Recovery Data Valid Data Setup Data Hold Delay to Next Write Byte Load Cycle WE Controlled Write Min. Max. 10 0 125 25 0 125 10 10 100 100 1 50 10 10 0.3 100 CE Controlled Write (4) Min. Max. 10 0 125 0 25 100 10 35 125 100 1 50 35 10 0.3 100 Units ms ns ns ns ns ns ns ns ns ns s ns ns s s 3873 PGM T08.1 WE Controlled Write Cycle tWC ADDRESS tAS tCS CE tAH tCH OE tOES WE tDV DATA IN DATA VALID tDS DATA OUT HIGH Z 3873 FHD F04 tWP tOEH tWPH tDH Note: (4) Due to the inclusion of the decoder IC on board the module the WE and CE write controlled timings will vary. When utilizing the CE controlled write operation all the hold timings must be extended by the worst case propagation delay of the decoder. For a WE controlled write operation CE must be a minimum 125ns to accommodate the additional setup time required. 12 XM28C040 CE Controlled Write Cycle tWC ADDRESS tAS CE tOES OE tOEH tCS WE tDV DATA IN DATA VALID tDS DATA OUT HIGH Z 3873 FHD F05 tAH tCW tWPH tCH tDH Page Write Cycle OE CE tWP WE tWPH *ADDRESS tBLC I/O BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 LAST BYTE BYTE n+2 tWC 3873 FHD F06 *For each successive write within the page write operation, A7-A18 should be the same or writes to an unknown address could occur. 13 XM28C040 DATA Polling Timing Diagram An An An ADDRESS CE WE tOEH OE tDW I/O7 DIN=X DOUT=X tWC DOUT=X tOES 3873 FHD F07 Toggle Bit Timing Diagram CE WE tOEH OE tDW I/O6 HIGH Z * tWC * Starting and ending state of I/O6 will vary, depending upon actual tWC. * tOES 3873 FHD F08 14 XM28C040 MultiPlane Architecture The design of the XM28C040 has implemented a multiplane architecture. That is, there are four independent 128K x 8 memory spaces or planes, each selected by its own chip enable input via the on-board decoder chip. This architecture can be utilized in a number of ways. Separate Data and Program Memory Spaces The multiplane concept allows the system to write to one plane of the module and still be able to read (continue executing code) from the module, utilizing any plane not performing a write operation. This concept of separate data and program spaces can be expanded by providing a simple off-module circuit that will disable writes to predetermined portions of memory. A very basic version is shown in the Functional Diagram. Whenever A18 is HIGH, the WE input is forced HIGH, write protecting one half the module. This half TABLE 1. ADDRESS TRANSLATION MATRIX Module Address Inputs A0-A7 System Address Lines Note: would be reserved for read only program store while the other half would be available for read and write data store. Expanded Sequential Page Lengths A standard system implementation would be decoding externally the module's chip enable and then wiring each address of the module to its corresponding address line in the system. This would effectively provide the system a memory organized as four separate memory planes with a sequential page address space of 256 bytes. In an application such as data logging, the most efficient method of logging the data is in a sequential manner. If the data come in bursts that exceed 256 bytes in length a longer page might be desirable. By swapping address lines externally the effective page length can be expanded to 1024 bytes. Refer to the table below for a matrix illustrating the various page length options. A8-A16 A8-A16 A9-A17 A10-A18 A17 A17 A8 A8 A18 A18 A18 A9 Page Size 256 512 1024 Effective No. of Planes 4 2 1 3873 PGM T09 A0-A7 A0-A7 A0-A7 The user should be aware the overall ICC of the module will increase as more individual components on the module are activated. 15 XM28C040 PACKAGING INFORMATION 32-PIN DUAL-IN-LINE MODULE USING STRETCHED CERAMIC LEADLESS CHIP CARRIERS ON SIDE BRAZED CERAMIC SUBSTRATE 0.610 (15.49) 0.590 (14.99) PIN 1 1.610 (40.89) 1.590 (40.39) 0.300 MAX. (7.62) .125 MIN. (3.18) 0.020 (0.51) 0.016 (0.41) 1.508 (38.30) 1.492 (37.90) TOL. NON. ACCUM. .100 .005 TYP. (2.54 .13) 0.604 (15.34) 0.596 (15.14) NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY 3926 ILL F47 16 XM28C040 ORDERING INFORMATION XM28C040: 512K X 8 CMOS E2PROM Module XM28C040 Device X X -X Access Time -20 = 200ns -25 = 250ns Blank = 300ns Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C M = Military = -55C to +125C MHR = Military High Rel Blank = 32-Lead Ceramic Module LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 17 |
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